Board-on-chip packages

ABSTRACT

The invention encompasses a board-on-chip package comprising an insulative substrate having circuitry thereon and an opening therethrough. A semiconductive-material-comprising die is adhered to the substrate and electrically connected to the circuitry with a plurality of electrical interconnects extending through the opening. A metal foil is in physical contact with at least a portion of the die. The invention also encompasses a method of forming a plurality of board-on-chip packages. An insulative substrate is provided. Such substrate has a repeating circuitry pattern thereon, and a plurality of openings therethrough. The openings are in a one-to-one correspondence with individual of the repeated circuitry patterns. A plurality of semiconductive-material-comprising dies are adhered to the substrate. Circuitry supported by the dies is electrically connected with the circuitry on the substrate utilizing a plurality of electrical interconnects extending through the openings. A metal foil is joined to the substrate and extended over the plurality of dies. The substrate and metal foil are cut to form singulated die packages comprising a single die, a portion of the substrate having a single repeated pattern of the circuitry, and a portion of the metal foil.

TECHNICAL FIELD

[0001] The invention pertains to board-on-chip packages, and to methodsof forming board-on-chip packages.

BACKGROUND OF THE INVENTION

[0002] A prior art method of forming a board-on-chip package (which canbe generally referred to as a die package) is described with referenceto FIGS. 1-5. Referring first to FIG. 1, such illustrates a fragment ofan assembly 10 comprising an insulative material substrate 12. Substrate12 can comprise, for example, a circuit board, such as the type known inthe art as FR-4™ (which can be obtained from Sumitomo of Japan), orBCBT™ (which can be obtained from Toppan of Japan.

[0003] Substrate 12 comprises a top surface 13 and slits 18 extendingtherethrough. Circuitry 16 is formed on top of surface 13. Circuitry 16and slits 18 form repeating patterns across top surface 13. Therepeating patterns define separate units 19, 21 and 23, each of whichultimately forms a separate board-on-chip package.

[0004] Referring to FIGS. 2-4, an enlarged segment of substrate 12,corresponding to unit 21, is shown in three different views. FIG. 2 is atop view similar to the view of FIG. 1, FIG. 3 is an end view, and FIG.4 is a view along the line 4-4 of FIG. 3. Substrate 12 is inverted inthe view of FIG. 3 relative to the view of FIGS. 1 and 2. Accordingly,surface 13 (referred to as a top surface in referring to FIGS. 1 and 2)is a bottom surface in the view of FIG. 3. In referring to FIG. 3,surface 13 will be referred to as a first surface.

[0005] Substrate 12 comprises a second surface 15 in opposing relationrelative to first surface 13. A semiconductive material-comprising chip(or die) 14 is adhered to surface 15 via a pair of adhesive strips 20.Strips 20 can comprise, for example, tape having a pair of opposingsurfaces 22 and 24, with adhesive being provided on both of suchopposing surfaces. Strips 20 typically comprise insulative material.Wire bonds 28 (only some of which are labeled in FIG. 2) extend fromcircuitry 16 and through slit 18 to electrically connect circuitry 16 tobonding pads 25 (only some of which are labeled in FIG. 2) associatedwith chip 14, and to accordingly electrically connect circuitry 16 withcircuitry (not shown) comprised by chip 14. (The wire bonds and bondingpads are not shown in FIG. 4 for purposes of clarity in theillustration.)

[0006]FIG. 5 illustrates further processing of the assembly 10.Specifically, FIG. 5 illustrates units 19 and 21 of FIG. 1 after a firstencapsulant 40 is provided over wire bonds 28, and a second encapsulant42 is provided over chips 14 associated with units 19 and 21. First andsecond encapsulants 40 and 42 can comprise the same material andpreferably comprise an insulative material, such as, for example, curedepoxy.

[0007] Conductive balls 31 are formed over portions of circuitry 16(shown in FIGS. 1 and 2) to form a ball grid array over circuitry 16.Such array can subsequently be utilized to form a plurality ofinterconnects from circuitry 16 to other circuitry (not shown).Conductive balls 31 can be formed of, for example, tin, copper or gold.

[0008] Substrate 12 is subjected to a singulation process whichseparates units 19 and 21 from one another, and thus forms individualboard-on-chip packages from units 19 and 21. The singulation process caninclude, for example, cutting through encapsulant 42 and substrate 12.

[0009] A problem which can be associated with board-on-chip packages isthat the chip can heat during use. The heating can damage electricalcomponents associated with the chip. It would be desirable to developalternative board-on-chip packages which alleviate such heating.

SUMMARY OF THE INVENTION

[0010] In one aspect, the invention encompasses a board-on-chip packagecomprising an insulative substrate having circuitry thereon and anopening therethrough. A semiconductive-material-comprising die isadhered to the substrate and electrically connected to the circuitrywith a plurality of electrical interconnects extending through theopening. A metal foil is in physical contact with at least a portion ofthe die.

[0011] In another aspect, the invention encompasses another embodimentboard-on-chip package comprising an insulative substrate havingcircuitry thereon and an opening therethrough. Asemiconductive-material-comprising die is adhered to the substrate andelectrically connected to the circuitry with a plurality of electricalinterconnects extending through the opening. The die has a first surfacefacing the substrate and a second surface in opposing relation to thefirst surface. The die further comprises a sidewall surface extendingbetween the first and second surfaces. A thermally conductive materialis in physical contact with at least one of the die first surface,second surface and sidewall surface. The thermally conductive materialhas a thermal conductivity under specified conditions equal to orgreater than the conductivity of elemental copper under the samespecified conditions.

[0012] In yet another aspect, the invention encompasses a method offorming a plurality of board-on-chip packages. An insulative substrateis provided. Such substrate has a repeating circuitry pattern thereon,and a plurality of openings therethrough. The openings are in aone-to-one correspondence with individual of the repeated circuitrypatterns. A plurality of semiconductive-material-comprising dies areadhered to the substrate. Circuitry supported by the dies iselectrically connected with the circuitry on the substrate utilizing aplurality of electrical interconnects extending through the openings. Ametal foil is joined to the substrate and extended over the plurality ofdies. The substrate and metal foil are cut to form singulated diepackages comprising a single die, a portion of the substrate having asingle repeated pattern of the circuitry, and a portion of the metalfoil.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0014]FIG. 1 is a diagrammatic, fragmentary view of a prior artsemiconductor assembly at a preliminary step of a die package formingprocess.

[0015]FIG. 2 is an expanded view of a portion of the FIG. 1 assembly.

[0016]FIG. 3 is a cross-sectional view along the line 3-3 of FIG. 2.

[0017]FIG. 4 is a cross-sectional view along the line 4-4 of FIG. 3.

[0018]FIG. 5 is a view of a portion of the FIG. 1 assembly shown beingsubjected to prior art processing subsequent to that of FIGS. 1-3.

[0019]FIG. 6 is a diagrammatic, cross-sectional view of a semiconductorassembly encompassed by the present invention.

[0020]FIG. 7 is a top view of the FIG. 6 structure.

[0021]FIG. 8 is a diagrammatic, cross-sectional view of a secondembodiment semiconductor assembly encompassed by the present invention.

[0022]FIG. 9 is a diagrammatic, cross-sectional view of a thirdembodiment semiconductor assembly encompassed by the present invention.

[0023]FIG. 10 is a diagrammatic, cross-sectional view of a fourthembodiment semiconductor assembly encompassed by the present invention.

[0024]FIG. 11 is a diagrammatic, cross-sectional view of a fifthembodiment semiconductor assembly encompassed by the present invention.

[0025]FIG. 12 is a diagrammatic, cross-sectional view of a sixthembodiment semiconductor assembly encompassed by the present invention.

[0026]FIG. 13 is a diagrammatic, cross-sectional view of a portion of asemiconductor assembly at a preliminary step of a method encompassed bythe present invention.

[0027]FIG. 14 is a view of the FIG. 13 assembly portion shown at aprocessing step subsequent to that of FIG. 13.

[0028]FIG. 15 is a top view of the assembly comprising the FIG. 14portion.

[0029]FIG. 16 is a cross-sectional side view of the FIG. 14 assemblyportion shown after singulation of units encompassed by the FIG. 14assembly portion.

[0030]FIG. 17 is a diagrammatic, cross-sectional view of a semiconductorassembly processed according to another embodiment method of the presentinvention.

[0031]FIG. 18 is a view of the FIG. 17 assembly shown at a processingstep subsequent to that of FIG. 17.

[0032]FIG. 19 is a view of a semiconductor assembly formed in accordancewith another method encompassed by the present invention.

[0033]FIG. 20 is a view of a semiconductor assembly formed in accordancewith yet another embodiment method encompassed by the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0035] A semiconductor assembly encompassed by the present invention isillustrated as assembly 50 in FIG. 6. Assembly 50 comprises aninsulative substrate 52 having an opening (or slit) 54 extendingtherethrough. Substrate 52 comprises a first surface 56 and a secondsurface 58 in opposing relation to first surface 56. Circuitry (such as,for example, the circuitry 16 described with reference to prior artFIG. 1) can be formed over first surface 56. Substrate 52 canaccordingly comprise a substrate identical to that described assubstrate 12 with reference to FIG. 1 of the prior art. In particularembodiments, substrate 52 can comprise a printed circuit board, such as,for example, either a board of the type known as FR-4 in the art, or ofthe type known as BCB in the art.

[0036] Conductive balls 60 are formed over first surface 56 of substrate52, and can comprise, for example, materials of the type described forprior art conductive balls 31 with reference to FIG. 5.

[0037] A semiconductive-material-comprising die (or chip) 62 is adheredto second surface 58 of substrate 52. Chip 62 comprises a first surface64 aligned to face toward second surface 58 of substrate 52. Chip 62further comprises a second surface 66 aligned to face away from secondsurface 58 of substrate 52. Additionally, chip 62 comprises a firstsidewall surface 68 and a second sidewall surface 70 in opposingrelation to first sidewall surface 68, with sidewall surfaces 68 and 70extending between the surfaces 64 and 66. Chip 62 can comprise aconstruction identical to that described above for chip 14 of the priorart.

[0038] Electrical interconnects 72 extend from chip 62, through opening54, and to the circuitry (not shown) on first surface 56 of substrate52. Interconnects 72 can comprise wire bonds identical to the wire bonds28 described above with reference to prior art FIGS. 1-5.

[0039] An encapsulant 74 is formed over electrical interconnects 72 andwithin opening 54. Encapsulant 74 can comprise materials identical tothose described for encapsulant 40 of the prior art.

[0040] A thermally conductive material 80 is formed over substrate 52and chip 62. Material 80 preferably has a thermal conductivity greaterthan or equal to that of elemental copper (with thermal conductivitybeing defined as the heat (in calories) transmitted per second through aplate 1 cm thick by about 1 cm² utilizing a temperature differential ofabout 1° C., the thermal conductivity of elemental copper beingunderstood to be about 1 calorie). The thermally conductive material 80can improve dissipation of heat from chip 62 relative to prior artboard-on-chip constructions, and can thus alleviate problems associatedwith chip heating.

[0041] In preferred embodiments, material 80 is a metal foil orconductive epoxy in physical contact with at least a portion of chip 62.Material 80 can comprise, for example, a metal foil selected from thegroup consisting of copper foil and aluminum foil. Alternatively,material 80 can comprise, for example, a silver-filled epoxy. Forpurposes of interpreting this disclosure and the claims that follow, ametal “foil” is to be understood as a metal sheet that is less than orequal to about 500 microns thick.

[0042] In the shown embodiment, thermally conductive material 80contacts substrate 52 at a first location 82 proximate first sidewall68, and at a second location 84 proximate second sidewall 70. Thermallyconductive material 80 extends across the first and second sidewalls andover second die surface 66, and is separated from first and secondsidewalls 68 and 70 by gaps 86 and 88, respectively. A material 90 isprovided within gaps 86 and 88 to adhere thermally conductive material80 to substrate 52. In the shown embodiment, gaps 86 and 88 arepredominately filled (actually entirely filled) with thermallyconductive material 90. Material 90 can comprise, for example, an epoxy,and preferably comprises an electrically conductive epoxy (such as, forexample, a silver-filled epoxy). A reason for utilizing the electricallyconductive epoxy is that electrically conductive materials arefrequently also thermally conductive and accordingly the electricallyconductive epoxy can help to dissociate heat from chip 62. It is to beunderstood, however, that material 90 can comprise an insulativematerial, and in particular embodiments can comprise a gas, such as, forexample, air.

[0043] It is noted that among the differences of the embodiment of FIG.6 relative to the prior art (such as, for example, the constructionshown in FIG. 3) is that tape 20 (FIG. 3) is eliminated in theembodiment of FIG. 6. Instead, chip 62 is adhered directly to substrate52. Such adhering of chip 62 directly to substrate 52 can beaccomplished by, for example, providing and curing an electricallyconductive epoxy between surface 64 of chip 62 and surface 58 ofsubstrate 52. Of course, tape (such as, for example, that shown in FIG.3) can also be utilized to adhere chip 62 with substrate 52 inembodiments of the present invention.

[0044]FIG. 7 shows a top view of assembly 50, and shows that thermallyconductive material 80 contacts an entirety of second surface 66 of die62, with die 62 being illustrated in phantom view beneath thermallyconductive material 80. In the shown configuration, die 62 comprises arectangular outer periphery having four sides (68, 70, 69 and 71), andconductive material 80 extends outwardly beyond the outer periphery ofthe die and contacts substrate 52 (FIG. 6) at locations proximate eachof the four sides.

[0045] Referring again to FIG. 6, it is noted that thermally conductivematerial 80 comprises a bend in extending from surface 58 of substrate52 to surface 66 of die 62. Because thermally conductive material 80comprises such bend, it can be advantageous to utilize flexiblematerials, such as, for example, thin thermally conductive foils for thethermally conductive material 80. A preferred thickness of a metal foilutilized for thermally conductive material 80 is from about 100 micronsto about 800 microns, with from about 150 microns to about 400 micronsbeing more preferred. Of course, the invention encompasses embodimentsin which material 80 does not flex, and in such embodiments it can beadvantageous to utilize a material 80 having a thickness greater than800 microns.

[0046] A second embodiment assembly of the present invention isdescribed with reference to FIG. 8. In referring to FIG. 8, similarnumbering will be utilized as was used above in describing theembodiment of FIG. 6 with the suffix “a” used to indicate structuresshown in FIG. 8.

[0047] Referring to FIG. 8, an assembly 50 a comprises an insulativesubstrate 52 a, and a chip 62 a. Chip 62 a comprises sidewalls 68 a and70 a. A thermally conductive material 80 a is formed over chip 62 a andsubstrate 52 a. The thermally conductive material 80 a of FIG. 8 cancomprise, for example, a metal foil, and can be adhered to substrate 52a and chip 62 a with conductive epoxy provided between the metal foiland surfaces of the chip and substrate.

[0048] Assembly 50 a is similar to the assembly 50 of FIG. 6, exceptthat the thermally conductive material 80 a contacts a predominantportion of the sidewalls 68 a and 70 a of chip 62 a, whereas thermallyconductive material 80 of the FIG. 6 assembly was separated from thepredominant portion of chip sidewalls 68 and 70 by gaps 86 and 88. It isnoted that the sidewalls 68 a and 70 a of FIG. 8 comprise respectivelengths corresponding to the distance between chip surface 64 a and chipsurface 66 a, and that in the shown embodiment thermally conductivematerial 80 a contacts an entirety of such lengths of sidewalls 68 a and70 a.

[0049] A third embodiment semiconductor assembly encompassed by thepresent invention is described with reference to FIG. 9. In referring toFIG. 9, similar numbering will be utilized as was used above indescribing FIG. 6, with the suffix “b” used to indicate structures shownin FIG. 9.

[0050]FIG. 9 shows an assembly 50 b comprising a substrate 52 b and asemiconductive-material-comprising chip 62 b over substrate 52 b. Chip62 b comprises a first surface 64 b aligned to face substrate 52 b. Chip62 b also comprises a second surface 66 b in opposing relation relativeto first surface 64 b, and accordingly aligned to face away fromsubstrate 52 b. Chip 62 b further comprises opposing sidewalls 68 b and70 b which extend between surfaces 64 b and 66 b.

[0051] A first thermally conductive material 80 b extends over chip 62 band substrate 52 b. First thermally conductive material 80 b cancomprise identical constructions as described above for material 80, andaccordingly could comprise, for example, a thin metal foil.

[0052] A second thermally conductive material 100 extends over substrate52 b and under chip 62 b. Second thermally conductive material 100 cancomprise an identical construction as first material 80 b, or adifferent construction. In preferred embodiments, thermally conductivematerial 100 and thermally conductive material 80 b will both comprisethin metal foils. In other embodiments, thermally conductive materials100 and 80 b can both comprise, for example, electrically conductiveepoxies, such as, for example, silver filled epoxies.

[0053] Thermally conductive material 80 b is separated from sidewalls 68b and 70 b of chip 62 b by gaps 86 b and 88 b. Such gaps can be leftvoid of conductive materials, or can be filled with a thermallyconductive material 90 b as shown. Such thermally conductive materialcan comprise, for example, an electrically conductive epoxy.

[0054] A fourth embodiment assembly of the present invention isdescribed with reference to FIG. 10. In referring to FIG. 10, similar 8numbering will be utilized as was used above in describing theembodiment of FIG. 9, with the suffix “c” used to indicate structurespertaining to FIG. 10.

[0055]FIG. 10 shows an assembly 50 c comprising a chip 62 c, a substrate52 c, a first thermally conductive material 100 c and a second thermallyconductive material 80 c. The assembly of FIG. 10 is similar to theassembly of FIG. 9 except that thermally conductive material 80 ccontacts a predominant portion of the sidewalls of chip 62 c, whereasthe thermally conductive material 80 b of FIG. 9 was spaced from apredominant portion of the sidewalls of chip 62 b.

[0056] A fifth embodiment of the present invention is described withreference to FIG. 11. In referring to FIG. 11, similar numbering will beused as was utilized above in describing the embodiment of FIG. 6, withthe suffix “d” used to indicate structures shown in FIG. 11.

[0057] An assembly 50 d is illustrated in FIG. 11, and such comprises achip 62 d over a substrate 52 d. Chip 62 d comprises a first surface 62d facing substrate 52 d, and a second surface 66 d in opposing relationrelative to first surface 62 d. A thermally conductive material 80 dextends over substrate 52 d and over a portion of chip 62 d. However, incontrast to the thermally conductive materials of FIGS. 6-10, thermallyconductive material 80 d contacts only a portion of the second surface66 d of chip 62 d. In the shown embodiment, thermally conductivematerial 80 d does not even cover a predominant portion (i.e., half) ofsecond surface 66 d. A prior art encapsulant (such as the encapsulantlabeled 42 in FIG. 5) can be provided over uncovered portions ofsubstrate 52 d and chip 62 d.

[0058] A sixth embodiment of the invention is described with referenceto FIG. 12. In referring to FIG. 12, similar numbering will be utilizedas was used above in describing the embodiment of FIG. 6, with thesuffix “e” used to indicate structures shown in FIG. 12.

[0059]FIG. 12 illustrates an assembly 50 e comprising an insulativesubstrate 52 e and a semiconductive-material-comprising chip 62 e.Substrate 52 e comprises a first surface 56 e having circuitry (notshown) formed thereon and a second surface 58 e in opposing relationrelative to first surface 56 e. A slit 54 e extends through substrate 52e, and a cavity 110 is formed within second surface 58 e and proximateslit 54 e. Chip 62 e is received within cavity 110. Chip 62 e comprisesa first (or inner) surface 64 e facing substrate 52 e and a second (orouter) surface 66 e in opposing relation relative to first surface 64 e.A thermally conductive material 80 e extends over chip 62 e andsubstrate 52 e. Thermally conductive material 80 e can comprise, forexample, a metal foil. It is noted that thermally conductive material 80e is not flexed over sidewalls of chip 62 e (compare the embodiments ofFIGS. 6-11). Accordingly, thermally conductive material 80 e can beformed of relatively non-flexible materials without adversely affectingprocessing utilized to form assembly 50 e. Thermally conductive material80 e can thus comprise a sheet of thermally conductive material having athickness of greater than about 800 microns, as well as comprisingrelatively flexible foils having thicknesses of less than about 800microns. The thermally conductive material utilized for sheet 80 e canbe selected from the group consisting of copper and aluminum. In theshown embodiment, chip 62 e is received entirely within cavity 110 andthermally conductive material 80 e extends over cavity 110 to enclosechip 62 e within the cavity. In other embodiments (not shown) chip 62 ecan have a portion extending outwardly of the cavity.

[0060] Chip 62 e and sheet 80 e can be adhered to one another, as wellas to substrate 52 e utilizing, for example, an electrically conductiveepoxy. In the shown embodiment, the sidewalls of chip 62 e are separatedfrom substrate 52 e by gaps 112 and 114. Such gaps can be left open, orcan be filled with a material, such as, for example, a thermallyconductive material. The thermally conductive material can comprise anelectrically conductive epoxy, such as, for example, silver-filledepoxy.

[0061] Referring to FIGS. 13-16, a method of forming an assembly of thepresent invention is described. In referring to FIGS. 13-16, similarnumbering will be used as was utilized above in describing theembodiment of FIG. 6, with the suffix “f” used to indicate structuresshown in FIGS. 13-16.

[0062] Referring first to FIG. 13, a portion of an assembly 200 isillustrated at a preliminary step of the described process. Assembly 200comprises an insulative substrate 52 f and a plurality of chips 62 fformed over substrate 52 f. Substrate 52 f can comprise, for example,the prior art substrate 12 described with reference to FIG. 1.

[0063] A plurality-of slits 54 f extend through substrate 52 f.Circuitry (not shown) is on a first surface 56 f of substrate 52 f. Suchcircuitry can correspond to, for example, the circuitry 16 of FIG. 1,and accordingly can be formed in a repeating pattern, with the patternhaving a one-to-one correspondence with slits 54 f. Chips 62 f areelectrically connected with the circuitry on surface 56 f withelectrical interconnects 72 f. Conductive balls 60 f are also associatedwith the circuitry on surface 56 f. Encapsulant 74 f is formed overelectrical interconnects 72 f and within gaps 54 f.

[0064] A thermally conductive material 80 f (preferably a metal foil) isformed over substrate 52 f and chips 62 f. Metal foil 80 f is adhered toone or both of substrate 52 f and chips 62 f. Foil 80 f can be adheredby, for example, utilizing an adhesive to bond foil 80 f to chips 62 fand substrate 52 f. An alternate method of adhering foil 80 f tosubstrate 52 f is to melt a portion of foil 80 f together with a portionof substrate 52 f. Such melting can be accomplished by, for example,directing a laser light 210 on the portions which are to be melted. Thelight can heat a localized region of metal foil 80 f together with alocalized region of substrate 52 f. The melted materials of foil 80 fand substrate 52 f can be subsequently cooled to effectively weld foil80 f to substrate 52 f. Although the laser light 210 is shown beingapplied in a direction which impacts foil 80 f instead of substrate 52f, it is to be understood that the laser light could be applied from anopposite direction (i.e., from a direction whereupon the light impingesupon substrate 52 f rather than metal foil 80 f), or from bothdirections simultaneously.

[0065] The chips 62 f of assembly 200 are separated from one another bygaps 220, and metal foil 80 f extends over gaps 220. Referring to FIG.14, metal foil 80 f is bent downwardly into gaps 220 to cause foil 80 fto contact substrate 52 f within gaps 220. In the shown embodimentwherein foil 80 f is bonded to substrate 52 f prior to being insertedwithin gaps 220, there is preferably an excess of foil provided betweenthe bonded portions to provide enough material 80 f to accommodate thebends formed in gaps 220. In alternative embodiments, material 80 f canbe bent into gaps 220 before the material is bonded to either substrate52 f or chips 62 f.

[0066] After material 80 f is bent into gaps 220, material 80 f ispreferably adhered to substrate 52 f within gaps 220. Such can beaccomplished by, for example, utilizing laser light 210 as shown in FIG.14. Alternatively, such can be accomplished by providing an adhesiveover substrate 52 within gaps 220 to adhere foil 80 f to substrate 52 f.

[0067]FIG. 15 is a top view of the assembly 200 which comprises theportion shown in FIG. 14. Such view shows that assembly 200 comprises asquare panel having 16 repeating patterns (i.e., four repeating patternson each side of the square panel). The panel can comprise a size of, forexample, from about 8″×8″ to about 12″×12″, such as, for example, a sizeof about 10″×10″. Chips 62 f are shown in phantom view in FIG. 15. Alsoshown in FIG. 15 are dashed lines 230 corresponding to locations whereinassembly 200 is cut to form singulated die packages (i.e., singulatedboard-on-chip packages). FIG. 15 further shows solid lines 240corresponding to locations wherein thermally conductive material 80 f isadhered to underlying substrate 52 f (FIG. 14).

[0068] Referring to FIG. 16, the portion of assembly 200 of FIG. 14 isshown after such portion is subjected to a cutting process whichseparates substrate 52 f into three singulated assemblies 250, 252 and254.

[0069] The embodiment described with reference to FIGS. 13-16 is merelyan exemplary embodiment for forming assemblies of the present invention.It is to be understood that the invention encompasses other methods offorming such assemblies. For instance, some of the steps shown in FIGS.13-16 can be done in an order other than that described with referenceto FIGS. 13-16. As an example, encapsulant 74 f and wire balls 60 f canbe provided after the bending of metal foil 80 f within gaps 220. Asanother example, metal foil 80 f can be bonded to at least portions ofsubstrate 52 f during or after the cutting described with reference toFIG. 16.

[0070] Another method of the present invention is described withreference to FIGS. 17 and 18. In referring to FIGS. 17 and 18, similarnumbering will be utilized as was used above in describing FIG. 6, withthe suffix “g” used to indicate structures shown in FIGS. 17 and 18.

[0071]FIG. 17 shows an assembly 50 g at an initial step of the method.Assembly 50 g comprises a substrate 52 g having a first surface 56 g anda second surface 58 g in opposing relation relative to surface 56 g.Circuitry (not shown) is formed on surface 56 g. Such circuitry cancomprise, for example, the circuitry 16 described with reference toprior art FIG. 1. A thermally conductive material 80 g is formed oversurface 58 g of substrate 52 g, and can be adhered to substrate 52 gutilizing, for example, a conductive epoxy. Thermally conductivematerial 80 g preferably comprises a flexible material, such as, forexample, a metal foil. Such metal foil can be selected from the groupconsisting of aluminum foil and copper foil.

[0072] An opening 54 g extends through thermally conductive material 80g and substrate 52 g. A semiconductive-material-comprising chip 62 g isprovided over thermally conductive material 80 g and across opening 54g. Chip 62 g comprises a first surface 64 g which faces substrate 52 gand a second surface 66 g in opposing relation relative to first surface64 g. Chip 62 g further comprises sidewalls 68 g and 70 g. Chip 62 g canbe adhered to thermally conductive material 80 g utilizing conductiveepoxy. Conductive interconnects 72 g extend through opening 54 g andelectrically connect chip 62 g with the circuitry formed on surface 56 gof substrate 52 g.

[0073] Referring to FIG. 18, thermally conductive material 80 g iswrapped around chip 62 g. In the shown embodiment, thermally conductivematerial 80 g is provided to be of sufficient length such that theconductive material overlaps over second surface 66 g of chip 62 g.

[0074]FIGS. 19 and 20 illustrate alternative assemblies 50 g which canbe formed utilizing thermally conductive material 80 g with differinglengths. Specifically, FIG. 19 illustrates an assembly 50 g whichresults from utilization of a material 80 g having a length such thatthe material forms a butt joint over surface 66 g of chip 62 g. FIG. 20illustrates an embodiment wherein thermally conductive material 80 g isof a length such that the material leaves a portion of surface 66 guncovered. A prior art encapsulant can be formed over the uncoveredportion.

[0075] The methods and apparatuses described in FIGS. 17-20 are merelyexemplary methods and apparatuses. The invention, of course, encompassesother methods and apparatuses. For instance, although the thermallyconductive material 80 g is shown formed against and along sidewalls 68g and 70 g of chip 62 g, it is to be understood that gaps analogous tothe gaps 86 and 88 of FIG. 6 could be left between the sidewalls and thethermally conductive material. Also, it is to be understood thatmaterials shown in FIGS. 17 and 18 could be provided after theprocessing of the conductive material 80 g described with reference toFIGS. 17 and 18. For instance, one or more of the encapsulant 74 g,interconnect 72 g, and conductive balls 60 g could be provided after theprocessing of conductive material 80 g of FIGS. 17 and 18, rather thanbefore such processing. Further, although the processing in FIGS. 17-20shows thermally conductive material 80 g initially provided on bothsides of slit 54 g, it is to be understood that the material could beinitially provided on only one side of the slit and wrapped eitherpartially or entirely around surfaces 66 g, 68 g and 70 g of chip 62 g.

[0076] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A board on chip package, comprising: an insulative substrate havingcircuitry thereon and an opening therethrough; asemiconductive-material-comprising die adhered to the substrate andelectrically connected to the circuitry with a plurality of electricalinterconnects extending through the opening; and a metal foil inphysical contact with at least a portion of the die.
 2. The board onchip package of claim 1 wherein the foil is adhered to the substratewith an electrically conductive epoxy.
 3. The board on chip package ofclaim 1 wherein the die has a first surface facing the substrate and asecond surface in opposing relation to the first surface, the foil beingin physical contact with only a portion of said second surface.
 4. Theboard on chip package of claim 1 wherein the die has a first surfacefacing the substrate and a second surface in opposing relation to thefirst surface, the foil being in physical contact with an entirety ofsaid second surface.
 5. The board on chip package of claim 1 wherein thedie has a first surface facing the substrate, a second surface inopposing relation to the first surface, and a sidewall between the firstand second surfaces, the foil being adhered to the substrate proximatethe sidewall and extending across the sidewall to physically contact thesecond surface.
 6. The board on chip package of claim 5 wherein thesidewall has a length, and wherein the foil physically contacts apredominate portion of the sidewall length.
 7. The board on chip packageof claim 5 wherein the sidewall has a length, and wherein the foil isspaced from a predominate portion of the sidewall length by a gap. 8.The board on chip package of claim 5 wherein the sidewall has a length,wherein the foil is spaced from a predominate portion of the sidewalllength by a gap, and wherein the gap has electrically conductive epoxyextending from the sidewall to the foil.
 9. The board on chip package ofclaim 5 wherein the sidewall has a length, wherein the foil is spacedfrom a predominate portion of the sidewall length by a gap, and whereinthe gap is filled with electrically conductive epoxy extending from thesidewall to the foil.
 10. The board on chip package of claim 1 whereinthe metal foil is selected from the group consisting of copper foil andaluminum foil.
 11. The board on chip package of claim 1 wherein the dieis adhered to the substrate with an electrically conductive epoxy.
 12. Aboard on chip package, comprising: an insulative substrate havingcircuitry thereon and an opening therethrough; asemiconductive-material-comprising die adhered to the substrate andelectrically connected to the circuitry with a plurality of electricalinterconnects extending through the opening; and a metal foil adhered toa portion of the die with an electrically conductive adhesive.
 13. Theboard on chip package of claim 12 wherein the die has a first surfacefacing the substrate and a second surface in opposing relation to thefirst surface, the foil being in physical contact with only a portion ofsaid second surface.
 14. The board on chip package of claim 12 whereinthe die has a first surface facing the substrate and a second surface inopposing relation to the first surface, the foil being in physicalcontact with an entirety of said second surface.
 15. The board on chippackage of claim 12 wherein the die has a first surface facing thesubstrate, a second surface in opposing relation to the first surface,and a sidewall between the first and second surfaces, the foil beingadhered to the substrate proximate the sidewall and extending across thesidewall to physically contact the second surface.
 16. The board on chippackage of claim 15 wherein the sidewall has a length, and wherein thefoil physically contacts a predominate portion of the sidewall length.17. The board on chip package of claim 15 wherein the sidewall has alength, and wherein the foil is spaced from a predominate portion of thesidewall length by a gap.
 18. The board on chip package of claim 15wherein the sidewall has a length, wherein the foil is spaced from apredominate portion of the sidewall length by a gap, and wherein the gaphas electrically conductive epoxy extending from the sidewall to thefoil.
 19. The board on chip package of claim 15 wherein the sidewall hasa length, wherein the foil is spaced from a predominate portion of thesidewall length by a gap, and wherein the gap is filled withelectrically conductive epoxy extending from the sidewall to the foil.20. The board on chip package of claim 12 wherein the metal foil isselected from the group consisting of copper foil and aluminum foil. 21.A board on chip package, comprising: an insulative substrate havingcircuitry thereon and an opening therethrough; asemiconductive-material-comprising die adhered to the substrate andelectrically connected to the circuitry with a plurality of electricalinterconnects extending through the opening, the die having a firstsurface facing the substrate, a second surface in opposing relation tothe first surface, and a sidewall surface extending between the firstand second surfaces; and a thermally conductive material in physicalcontact with at least two of the die first surface, second surface andsidewall surface; the thermally conductive material having a thermalconductivity under specified conditions equal to or greater than thethermal conductivity of elemental copper under the same specifiedconditions.
 22. The board on chip package of claim 21 wherein thethermally conductive material comprises a silver-filled epoxy.
 23. Theboard on chip package of claim 21 wherein the thermally conductivematerial comprises a metal foil.
 24. The board on chip package of claim21 wherein the thermally conductive material comprises a materialselected from the group consisting of aluminum foil and copper foil. 25.The board on chip package of claim 21 wherein the thermally conductivematerial is in physical contact with the second surface.
 26. The boardon chip package of claim 21 wherein the thermally conductive material isin physical contact with the sidewall and the second surface.
 27. Theboard on chip package of claim 21 wherein the thermally conductivematerial is in physical contact with the sidewall, the first surface andthe second surface.
 28. A board on chip package, comprising: aninsulative substrate having circuitry thereon and an openingtherethrough, the substrate comprising a first surface and a secondsurface in opposing relation to the first surface, the circuitry beingon the first surface, the substrate further comprising a cavityextending into the second surface and proximate the opening; asemiconductive-material-comprising die received within the cavity andelectrically connected to the circuitry with a plurality of conductiveinterconnects extending through the opening, the die having an innersurface facing the substrate and an outer surface in opposing relationto the inner surface; and a metal sheet in physical contact with atleast a portion of the die outer surface.
 29. The board on chip packageof claim 28 wherein the die is entirely received in the cavity inwardlyof the second surface of the substrate, and wherein the sheet extendsalong the second surface of the substrate and over the cavity to enclosethe die in the cavity.
 30. The board on chip package of claim 28 whereinthe metal sheet is selected from the group consisting of copper foil andaluminum foil.
 31. The board on chip package of claim 28 wherein the dieis adhered to the substrate with an electrically conductive epoxy.
 32. Aboard on chip package, comprising: an insulative substrate having a pairof opposing surfaces and an opening extending therethrough, the opposingsurfaces being a first surface and a second surface; circuitry on thefirst surface of the substrate; a semiconductive-material-comprising dieadhered to the second surface of the substrate, the die having a pair ofopposing surfaces, one of the die opposing surfaces being a first diesurface and being aligned to face toward the second surface of thesubstrate, the other die surface being a second die surface and beingaligned to face away from the second surface of the substrate, the diefurther comprising first and second opposing sidewalls extending betweenthe first and second surfaces; electrical interconnects extending fromthe die, through the opening and to the circuitry; a metal foilcontacting the substrate at a first location proximate the firstsidewall and a second location proximate the second sidewall, the metalfoil extending across the first and second sidewalls and over the seconddie surface; the metal foil physically contacting a predominate portionof the second die surface.
 33. The board on chip package of claim 32wherein the metal foil comprises a foil selected from the groupconsisting of aluminum foil and copper foil.
 34. The board on chippackage of claim 32 wherein the foil is adhered to the substrate with anelectrically conductive epoxy.
 35. The board on chip package of claim 32wherein the foil is in physical contact with only a portion of thesecond die surface.
 36. The board on chip package of claim 32 whereinthe foil is in physical contact with an entirety of the second diesurface.
 37. The board on chip package of claim 32 wherein the sidewallhas a length, and wherein the foil physically contacts a predominateportion of the sidewall length.
 38. The board on chip package of claim32 wherein the sidewall has a length, and wherein the foil is spacedfrom a predominate portion of the sidewall length by a gap.
 39. Theboard on chip package of claim 32 wherein the sidewall has a length,wherein the foil is spaced from a predominate portion of the sidewalllength by a gap, and wherein the gap has electrically conductive epoxyextending from the sidewall to the foil.
 40. The board on chip packageof claim 32 wherein the die is adhered to the substrate with anelectrically conductive epoxy.
 41. The board on chip package of claim 32wherein the die comprises a rectangular outer periphery having foursides, wherein the metal foil extends outwardly beyond the outerperiphery of the die and contacts the substrate at locations proximateeach of the four sides.
 42. A method of forming a board on chip package,comprising: providing an insulative substrate having circuitry thereonand an opening therethrough; adhering asemiconductive-material-comprising die to the substrate with anelectrically conductive adhesive, the die having circuitry supportedthereby; and electrically connecting the circuitry supported by the dieto the circuitry on the substrate with a plurality of electricalinterconnects extending through the opening.
 43. The method of claim 42wherein the electrically conductive adhesive comprises silver-filledepoxy.
 44. The method of claim 42 wherein the die has a surface, andfurther comprising placing a metal foil in physical contact with atleast a portion of the die surface.
 45. A method of forming a board onchip package, comprising: providing an insulative substrate havingcircuitry thereon and an opening therethrough; adhering asemiconductive-material-comprising die to the substrate and electricallyconnecting circuitry supported by the die with the circuitry on thesubstrate utilizing a plurality of electrical interconnects extendingthrough the opening; and joining a metal foil to the substrate, themetal foil having a segment extending over the die and in physicalcontact with at least a portion of the die.
 46. The method of claim 45wherein the joining the metal foil to the substrate comprises weldingthe metal foil to the substrate by melting a portion of the metal foilwith a portion of the substrate.
 47. The method of claim 46 wherein themelting is accomplished with a laser.
 48. The method of claim 45 whereinthe joining the metal foil to the substrate comprises adhering the metalfoil to the substrate with an electrically conductive epoxy.
 49. Themethod of claim 45 wherein the die has a first surface facing thesubstrate and a second surface in opposing relation to the firstsurface, the foil being in physical contact with only a portion of saidsecond surface.
 50. The method of claim 45 wherein the die has a firstsurface facing the substrate and a second surface in opposing relationto the first surface, the foil being in physical contact with anentirety of said second surface.
 51. The method of claim 45 wherein thedie has a first surface facing the substrate, a second surface inopposing relation to the first surface, and a sidewall between the firstand second surfaces, the foil being joined to the substrate proximatethe sidewall and extending across the sidewall to physically contact thesecond surface.
 52. The method of claim 51 wherein the sidewall has alength, and wherein the foil physically contacts a predominate portionof the sidewall length.
 53. The method of claim 51 wherein the sidewallhas a length, and wherein the foil is spaced from a predominate portionof the sidewall length by a gap.
 54. The method of claim 51 wherein thesidewall has a length, wherein the foil is spaced from a predominateportion of the sidewall length by a gap, and wherein the gap haselectrically conductive epoxy extending from the sidewall to the foil.55. The method of claim 45 wherein the metal foil is selected from thegroup consisting of copper foil and aluminum foil.
 56. The method ofclaim 45 further comprising adhering the die to the substrate with anelectrically conductive epoxy.
 57. A method of forming a board on chippackage, comprising: providing an insulative substrate having circuitrythereon and an opening therethrough, the substrate having a pair ofopposing surfaces, the surfaces being a first surface and a secondsurface, the circuitry being on the first surface; adhering a metal foilto the second surface; adhering a semiconductive-material-comprising dieto the metal foil, the die having circuitry supported thereby; andelectrically connecting the circuitry supported by the die to thecircuitry on the substrate with a plurality of electrical interconnectsextending through the opening.
 58. The method of claim 57 wherein thedie has a pair of opposing sides; wherein the die covers a portion ofthe metal foil and leaves an other portion of the metal foil extendingoutwardly beyond one of the opposing sides of the die; and furthercomprising wrapping at least some of said other portion of the foilalong the at least one of the opposing sides of the die.
 59. The methodof claim 58 wherein the die comprises a first surface facing thesubstrate and second surface in opposed relation to the first surface,the other portion of the foil being wrapped along both of the opposingsides of the die and over the second surface of the die.
 60. The methodof claim 57 wherein the die has a pair of opposing sides; wherein thedie covers a portion of the metal foil and leaves a pair of otherportions of the metal foil extending outwardly beyond the opposing sidesof the die; said pair of other portions comprising a first other portionwhich extends outwardly of the first side of the die, and a second otherportion which extends outwardly of the second side of the die; themethod further comprising wrapping the first other portion of the foilalong the first of the opposing sides of the die, and wrapping thesecond other portion of the foil along the second of the opposing sidesof the die.
 61. The method of claim 60 wherein die comprises a firstsurface facing the substrate and second surface in opposed relation tothe first surface, the first and second other portions of the foiljoining one another over the second surface of the die.
 62. The methodof claim 61 wherein the first and second other portions overlap oneanother over the second surface of the die.
 63. A method of forming aboard on chip package, comprising: providing an insulative substratehaving circuitry thereon and an opening therethrough, the substratecomprising a first surface and a second surface in opposing relation tothe first surface, the circuitry being on the first surface, thesubstrate further comprising a cavity extending into the second surfaceand proximate the opening; placing a semiconductive-material-comprisingdie within the cavity and electrically connecting circuitry supported bythe die to the circuitry on the substrate first surface with a pluralityof conductive interconnects extending through the opening, the diehaving an inner surface facing the substrate and an outer surface inopposing relation to the inner surface; and placing a metal sheetoutwardly of the die and in physical contact with at least a portion ofthe die outer surface.
 64. The method of claim 63 wherein the die has aportion extending outwardly of the cavity, and wherein the sheet extendsalong the second surface of the substrate and over the portion of thedie extending outwardly of the cavity, the method further comprisingbonding the sheet to the second surface of the substrate.
 65. The methodof claim 63 wherein the die is entirely received in the cavity inwardlyof the second surface of the substrate, and wherein the sheet extendsalong the second surface of the substrate and over the cavity to enclosethe die in the cavity, the method further comprising bonding the sheetto the second surface of the substrate.
 66. The method of claim 63wherein the metal sheet is selected from the group consisting of copperfoil and aluminum foil.
 67. The method of claim 63 further comprisingadhering the die to the substrate with an electrically conductive epoxy.68. A method of forming a plurality of board on chip packages,comprising: providing an insulative substrate having a repeatingcircuitry pattern thereon and a plurality of openings therethrough, theopenings being in one-to-one correspondence with individual of therepeated circuitry patterns; adhering a plurality ofsemiconductive-material-comprising dies to the substrate andelectrically connecting circuitry supported by the dies with thecircuitry on the substrate utilizing a plurality of electricalinterconnects extending through the openings; joining a metal foil tothe substrate and extending the metal foil over the plurality of dies;and cutting the substrate and metal foil to form singulated die packagescomprising a single die, a portion of the substrate having a singlerepeated pattern of the circuitry, and a portion of the metal foil. 69.The method of claim 68 wherein the substrate comprises areas between thedie, and wherein the metal foil is bonded to such areas before thecutting of the substrate.
 70. The method of claim 69 wherein the bondingcomprises welding the metal foil to the substrate by melting a portionof the metal foil and a portion of the substrate.
 71. The method ofclaim 69 wherein the bonding comprises adhering the metal foil to thesubstrate with an adhesive.
 72. The method of claim 69 wherein thebonding comprises adhering the metal foil to the substrate with anelectrically conductive adhesive.
 73. The method of claim 69 wherein thebonding comprises adhering the metal foil to the substrate withsilver-filled epoxy.
 74. The method of claim 68 wherein the substratecomprises areas between the die, and wherein the metal foil is notbonded to said areas until during or after the cutting of the substrate.